700 questions
0
votes
0
answers
40
views
Can I insert a folder (directory) instead of a file as a BlackBox in Chipyard?
I am trying to configure an MMIO Peripheral (= MMIO Accelerator, 11page) consisting of a 4x4 NoC in Chipyard. In this process, I would like to insert a SystemVerilog-based NoC as a BlackBox. However, ...
1
vote
0
answers
49
views
How do I peek a Bundle in ChiselSim?
I'm trying to test a circuit with ChiselSim. The input to the circuit is a Bundle (without nesting) which I can poke without any problem, but when I try to peek the output of the same type I get an ...
- 148
1
vote
1
answer
102
views
To what extent can I expect the original FIRRTL compiler to optimize?
For now I am still using the final release of the original FIRRTL compiler that was archived in 2024.
I am using to software compilers going to great lengths to optimize code, performing constant ...
- 1,925
0
votes
0
answers
37
views
mill debugger intellij in Xiangshan project
I'm trying to debug the XiangShan RISC-V SoC project using IntelliJ IDEA with Mill and BSP.
I've followed all recommended steps (scala, the mill build tool, and the IntelliJ debugger) but breakpoints ...
0
votes
0
answers
57
views
Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface. This MMIO device is intended to be a slave and the rocket-core as the master. For this, I created a ...
- 182
0
votes
0
answers
41
views
Parameterization in Gemmini
I wanted to explore the parameterization in Gemmini. So I modified the mesh row and mesh column of GemminiConfigs.scala and Configs.scala like this:
previously mesh row and mesh column was 16, I ...
1
vote
1
answer
48
views
How do I initialize a Vec inside a Bundle literal in Chisel?
I'm trying to test a module which takes as input a UInt that follows the structure of this Bundle:
class Sample(n_attr: Int, n_classes: Int, n_depths: Int, info_bit: Int, tree_bit: Int) extends Bundle{...
- 148
1
vote
0
answers
38
views
Adding an AttributeAnnotation to a SyncReadMem object in latest Chisel versions
I am trying to annotate a SyncReadMem object with with a verilog attribute in the newer versions of Chisel (>3.6.1). I'm using Chisel mostly for FPGA development, and so for the different FPGA ...
0
votes
1
answer
199
views
In Chisel3, how to add `mark_debug = "true"` attribute to an internal signal in the output SystemVerilog file?
As stated in the title, I want to easily make any internal signals in my design to be available for debugging in Vivado (mostly ILA). In version 3.5.3 I was able to use a snippet to do it, however in ...
0
votes
0
answers
23
views
Chisel3 VCD waveform dump does not update a signal
I am simulating a simple AND gate in Chisel3/Scala.
import chisel3._
class ChiselPractice extends Module {
val io = IO(new Bundle {
val in1 = Input(Bool())
val in2 = Input(Bool())
val ...
- 311
0
votes
1
answer
93
views
How to disable `ifdef FIRRTL_BEFORE_INITIAL` in Chisel?
When generating code, I get garbage like
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
initial begin
automatic ...
1
vote
1
answer
84
views
In RISCV, is Each thread has a own PC value in multithreading Program?
Im currently working on a Hard ware for Data Race detect
So I track each instructions and made history table for race detect.
I made C program for Intended data race and Track instructions by PC value
...
- 11
2
votes
1
answer
609
views
How to generate Verilog rather than SystemVerilog from Chisel?
Here is my GCD.scala
package gcd
import chisel3._
class GCD extends Module {
val io = IO(new Bundle {
val value1 = Input(UInt(16.W))
val value2 = Input(UInt(16.W))
val ...
- 23
1
vote
0
answers
132
views
How to obtain emulator binary in latest rocket-chip using mill and chisel 5.0.0?
I've setup Chisel 5.0.0 and firtool as I explained in this other question. I also installed successfully mill and rocket-tools as instructed here and here.
This prepared the stage for getting the ...
- 319
0
votes
0
answers
42
views
error message chisel when call a module in another module
I have defined the class fu_data_t and cap_result_t in a scala file, which is used in the class crevokeModule in another scala file. Then, crevokeModule is used in the class AluDataModule. Finally, ...
- 1
2
votes
0
answers
93
views
Chisel Template Not Functioning Windows 11 - Cannot run program "which": CreateProcess error=2, The system cannot find the file specified
After having cloned the template project for Chisel (https://github.com/chipsalliance/chisel-template) I tried running sbt test, and I got the following error in the file /src/test/scala/gcd/GCDSpec:
&...
- 47
3
votes
1
answer
99
views
Using each delayed flop states in chisel ShiftRegister
I am writing chisel for the following FIR circut (specifically to understand ShiftRegister in chisel as this can be done easily using NextReg in chisel).
I have written this code:
class My4ElementFir(...
1
vote
0
answers
343
views
How can i generate vcd file with recent version of Chisel?
I used to generate the vcd file through chiseltest like below.
import chisel3._
import chiseltest._
import org.scalatest.flatspec.AnyFlatSpec
class MyModuleSpec extends AnyFlatSpec with ...
- 69
0
votes
1
answer
48
views
How to override a Chisel constant with type of Vec?
Here's a class named RequestBuffer.
class RequestBuffer(flow: Boolean = true, entries: Int = 4)(implicit p: Parameters) extends L2Module {
val buffer = RegInit(VecInit(Seq.fill(entries)(0.U.asTypeOf(...
- 1
2
votes
1
answer
669
views
Generating verilog file for rocket chip
I am a beginner working with rocket chip generator for my project but I am not able to generate the verilog file for it and facing this error. I am using an apple M1 chip macOS. I started with cloning ...
1
vote
0
answers
202
views
In chisel6.2.0, how to use hex file to init memory and test it?
I have the same problem as this one: in-chisel-3-how-to-initialize-memory-test-code-with-text-file, my test code indicates that loadMemoryFromFile makes no sense. I think my filepath is correct, but ...
- 11
1
vote
0
answers
134
views
With Chisel How to avoid verilog file list at the end of generated file when using BlackBox?
I'm using Blackbox with setInLine function in a design.
class ResetGenEna(delayClk: Int) extends BlackBox with HasBlackBoxInline {
val io = IO(new Bundle {
val clk = Input(Clock())
val ena =...
- 3,901
1
vote
2
answers
85
views
Is it good thing to use `reduce(_ ## _) ` for IndexedSeq to UInt conversion in Chisel?
For a little Chisel project I'm using reduce(_ ## _) function to convert an IndexedSeq to UInt.
class PdChain(n: Int = 4) extends Module {
val io = IO(new Bundle {
val count = Output(UInt(n.W))
...
- 3,901
1
vote
1
answer
51
views
How to propagate a value from a Module upwards
I have two modules, one has a latency of x clock cycles, the other one has a latency of y clock cycles.
I'd like to tie the latency to each of these modules, so that when I instantiate the module in e....
- 13
2
votes
1
answer
157
views
Issues with creating an n-to-1 multiplexer in Chisel
I am currently working on creating an n-to-1 multiplexer using Chisel, where nr_m equals 2. I have written some code, but I am encountering issues when trying to generate Verilog. Here is the code I ...
- 21
1
vote
1
answer
87
views
a chisel problem about some value only read-only
I don't get any errors during compilation, but when I try to run the code, it fails. I'm not sure why this error is happening. Previously, when I was writing an RCA(code in the under), I encountered a ...
- 11
2
votes
1
answer
177
views
In FPGA, why counter with full adder raw implementation have better clock performance than infered addition '+'?
I'm testing counter and addition performances on ICE40 and Gatemate FPGAs.
I wrote counter in two differents way :
NaturalCounter using the operator '+' of chisel (view source):
// Natural counter ...
- 3,901
1
vote
1
answer
61
views
Variable sized type in Chisel
I have the following code that compiles:
class S extends Bundle {
val channels = VecInit.fill(7)(UInt(32.W))
}
class D extends Module {
val v = IO(Flipped(Decoupled(new S)))
v.ready := true.B
}
...
- 361
1
vote
1
answer
82
views
Using Chisel Submodule within another Module: Cannot assign variables to the io input
I am trying to create a simple counter, which counts how many seconds have passed up until and including some max_count_S.
To simplify the process I have first created a "signal" counter, ...
- 47
0
votes
1
answer
101
views
The problem with AyncFIFO with two clock sources written in Chisel 5.0
I wrote a AsyncFIFO in Chisel. Since Chisel-tester doesn't support multiple clock source, I wrote another shell to encapsulate the fifo. However, I encountered a problem in testing the empty condition....
0
votes
1
answer
164
views
sbt test does not work and all the tests fail
I have installed rocket-chip and it needs chisel to compile i have also downloaded chisel , but when i run sbt test all the tests fail, am i doing something wrong . is there an alternative for sbt ...
- 3
0
votes
1
answer
108
views
How to export TileLink node to LazyModule's output and generate respective verilog file
I am trying to create a simple module with tilelink client connected to modules output. How to do it? Have been trying to figure it out for 20 hours at this, I am completly lost.
I am trying the ...
- 1
1
vote
1
answer
1k
views
Type Casting in Chisel: Converting UInt to Int
I am working on a Chisel project and encountered an issue related to converting UInt to Int. I have tried using the litValue method, but it's giving me a None.get error when executing my code. I need ...
0
votes
0
answers
47
views
Select a single enq/deq interface from a vector in IO to connect to a module in Chisel3
I have a module with a vector of Enq/Deq interfaces as IO. Internally, I instantiate a module with a single Enq/Deq interface. I want to be able to input an index that will select Enq/Deq input ...
- 4,758
0
votes
1
answer
155
views
Chisel: Define functions that operate on user defined Bundle types
I have a Bundle type containing a 2D vec:
def myBundle extends Bundle {
val v = Vec(4, Vec( 4, UInt()))
// etc ...
}
I want to define a hardware generating function which operates on myBundle and ...
- 502
0
votes
1
answer
89
views
Chisel IO bundle that works for any width for a given Chisel hardware type
In chisel you can have a hardware generating function like the following:
def hw_func(x: Vec[UInt]) : Vec[UInt] = x // useless I know
Where the formal argument and return value do not specify the ...
- 502
0
votes
2
answers
245
views
Using subrepo for Chisel project errs
I am trying to use the AsyncQueue subrepo (https://github.com/ucb-bar/asyncqueue) in my own project, much as the ClockDividerDemo in Chisel Multiclock Demos (https://github.com/edwardcwang/chisel-...
- 25
0
votes
1
answer
81
views
Exception in thread "main" chisel3.internal.ChiselException: Cannot reassign to read-only AluAccu.?: OpResult[UInt<2>]
I want use chisel to achieve addr in alu.
The verilog code like this
assign {Carry,Result} = A + t_no_Cin + Cin;
So I wirte the chisel code like this
Cat(io.carry, result_temp) := (io.din1 + t_no_cin ...
- 1
2
votes
1
answer
196
views
How to deal with ActiveLow Reset / change implicit clock frequency?
How to config implicit clock from 100MHz to 50 MHz(So its show up in my WaveGTK Sim)?
How to deal with Active Low / Active High?
ex.
val io = IO(new Bundle() {
val activeLowReset = Input(Bool())....
- 21
2
votes
1
answer
167
views
Serializer in Chisel: Register printf dont seem to make sense
I'm trying build a simple rx serializer in Chisel, accepting a 1-bit serial datastream. The assumption is that the datastream clockrate is significantly lower than the internal clockrate.
I am using a ...
- 25
3
votes
1
answer
399
views
chisel 5.0.0-RC1 and chiseltest
I'm attempting to upgrade a chisel 3.6.0 project to 5.0.0-RC1, and according to the docs it looks as though chiseltest is not recommended for new projects. On a hunch I did also try to add a ...
- 51
3
votes
1
answer
129
views
Access Chisel Module Variables at emitVerilog
I have a Chisel module, that has lots of submodules. The top module is configured with a set of parameters. The submodules have their configuration too; based on the input parameters and some ...
- 33
0
votes
1
answer
67
views
How is data width determined for load/store instructions in Rocket Core?
I'm working on a project where we need to modify a Rocket-chip core with new instructions.
We're wondering: how does data width for load/store instructions is determined ?
For instance, LB/LH/LU have ...
- 1
0
votes
1
answer
131
views
Rocket Chip - Access Exception on Page Table Walk
I am trying to integrate a RoCC accelerator with RocketChip / Chipyard. Given a virtual address, the accelerator should translate it to a physical address, read some data from memory and then start a ...
- 33
3
votes
2
answers
274
views
Exposing Simulation-only behavior in Chisel3
I want to expose certain signals only during simulation (for performance monitoring purposes, etc...) that can be used during the debug process for various purposes. I could use the dontTouch ...
- 637
2
votes
1
answer
166
views
How to bulk connect IO bundles in chisel? How does BiConnect work?
I struggle to understand the documentation around the <> operator in chisel but I have managed to something like this successfully, so I thought I had some understanding of it:
fetchStage....
- 67
1
vote
0
answers
63
views
`SInt * SInt` became `UInt * SInt` in chisel
I'm writing a convolution neural network accelerator. In the conv unit, I choose to implement convolution with 3 1D FIRs. In the testing stage, I got UInt*SInt multiply results instead of SInt*SInt. ...
- 11
1
vote
1
answer
370
views
using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language
I want to use rocket chip to generate a axi4crossbar with 2 slave ports and 1 master port, here is my chisel source code
package empty
import chipsalliance.rocketchip.config.{Config, Parameters}
...
- 25
1
vote
0
answers
225
views
Exception in thread "main" chisel3.package$ChiselException: Unable to locate the elaborated circuit, did chisel3.stage.phases.Elaborate run correctly
While setting up the Chisel in my linux environment and running a small and_gate test .
I am getting error like this:
[error] Exception in thread "main" chisel3.package$ChiselException: ...
0
votes
1
answer
68
views
How to return the corresponding string in chisel?
I want to return the name of the corresponding uop according to the ordinal number of the uop.
I have tried various methods without success. I feel that there is a problem with the type usage of ...
- 816