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I have a Bundle type containing a 2D vec:

def myBundle extends Bundle {
  val v = Vec(4, Vec( 4, UInt()))
  // etc ...
}

I want to define a hardware generating function which operates on myBundle and returns a myBundle like so:

def elementwise_add(x: myBundle, y: myBundle): MyBundle {
  val result = new MyBundle
  for(i <- 0 until 4)
    for(j <- 0 until 4)
      result.v(i)(j) = x.v(i)(j) + y.v(i)(j)
   return result
}

However if I define this, Chisel throws an error during compile that: "value update is not a member of chisel3.Vec[chisel3.UInt] did you mean updated?"

How should I define this function (and others like it) so that it generates the hardware I am trying to generate here?

(Note: Vec here is important in this case because I want to be able to address myBundle.v with hardware signals)

1 Answer 1

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Change:

def elementwise_add(x: myBundle, y: myBundle): MyBundle {
  val result = new MyBundle
  for(i <- 0 until 4)
    for(j <- 0 until 4)
      result.v(i)(j) = x.v(i)(j) + y.v(i)(j)
   return result
}

to:

def elementwise_add(x: myBundle, y: myBundle): MyBundle {
  val result = new MyBundle
  for(i <- 0 until 4)
    for(j <- 0 until 4)
      result.v(i)(j) := x.v(i)(j) + y.v(i)(j)
   return result
}

(use chisel assign(:=) operator rather than Scala =) And make sure you are using Chisel 5.0 or greater (I was on 3.5.6) and this code works as expected.

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