I have a Bundle type containing a 2D vec:
def myBundle extends Bundle {
val v = Vec(4, Vec( 4, UInt()))
// etc ...
}
I want to define a hardware generating function which operates on myBundle and returns a myBundle like so:
def elementwise_add(x: myBundle, y: myBundle): MyBundle {
val result = new MyBundle
for(i <- 0 until 4)
for(j <- 0 until 4)
result.v(i)(j) = x.v(i)(j) + y.v(i)(j)
return result
}
However if I define this, Chisel throws an error during compile that: "value update is not a member of chisel3.Vec[chisel3.UInt] did you mean updated?"
How should I define this function (and others like it) so that it generates the hardware I am trying to generate here?
(Note: Vec here is important in this case because I want to be able to address myBundle.v with hardware signals)