1,431 questions
1
vote
0
answers
58
views
Override __memcmpeq with --wrap
I'm unable to override the compiler-generated __memcmpeq function using --wrap=__memcmpeq, which is a shortcut for boolean usage of memcmp (but is otherwise the same).
rustflags = ["-C", &...
- 567
3
votes
0
answers
83
views
After enabling an interrupt via CSRRW in RISC-V, how many instructions may execute before trap entry?
In RISC-V machine mode, when you issue a csrrw that sets a bit in mie (i.e. enabling an interrupt that is already pending), must the very next instruction immediately branch to the interrupt handler? ...
- 305
0
votes
0
answers
54
views
DISAS_NORETURNs causing errors while attempting to intercept QEMU syscalls by tweaking the ecall() function
I am trying to modify the ecall behavior in QEMU usermode simulation, so that i can intercept system calls.
The way i intend to do it is by reading states from the CPURISCVState with tcg_gen_ld_tl -- ...
0
votes
0
answers
68
views
How to setup approriate configs for single-core rocket-chip Gemmini Accelerator?
I'm buiding a single-core rocket chip, which use an Gemmini interface to do systollic array, and I use board Arty-Z7 to run demo on FPGA. My problem here is I don't know how to choose a suitable ...
- 1
0
votes
0
answers
137
views
Nightly Rust #[unsafe(naked)] function leads to undefined symbol linker error in --release mode on RISC-V
I am writing a hobby OS kernel in Rust for the riscv64gc-unknown-none-elf target. I have defined my trap_entry, as a #[unsafe(naked)] function within a Rust module.
When I compile in release mode (...
- 1
1
vote
1
answer
100
views
Risc-v compressed instruction alignment [closed]
When supported, compressed instructions (RVC) bring a relaxation of code address alignment from 4 to 2 bytes.
They also bring the possibility to intermix compressed and non-compressed instructions.
...
- 3,500
0
votes
0
answers
92
views
How does a failed spinlock CAS affect out-of-order speculation and RMW reordering on weak memory architectures?
I’m trying to understand how speculative execution interacts with weak memory models (ARM/Power) in the context of a spinlock implemented with a plain CAS. Example:
// Spinlock acquisition attempt
if (...
- 1,385
1
vote
0
answers
124
views
RISC-V a1 register assumptions after ecall execution
As explained here it's clear to me that user-space calling conventions don't apply when dealing with kernel-space system call execution, so basically no register is clobbered after an ecall ...
2
votes
0
answers
87
views
RISC-V bare-metal simulation problem, increasing .rodata array size causes hang during DMA
I am trying to write data starting at a specific address (0x88000000) of the memory (simulated DRAM size is 256 MiB), once all data is written, the DMA unit is programmed using the MMIO registers. The ...
- 182
-1
votes
1
answer
132
views
LLVM generates stack usage on simple RISC-V function where GCC doesn't
I have a simple function:
extern "C" Variant test_bool(bool arg) {
return arg;
}
Built with mostly standard settings (I removed part of the paths):
zig c++ -target riscv64-linux-musl -I/...
- 567
0
votes
1
answer
112
views
RISC-V GCC Force Linker Relaxation with GP Register to Address Static Data
I'm writing a bare-metal firmware for a virtual RISC-V SoC. Below is code that communicates with a physical device on the SoC and it is using constant data from the my_data array that sits in ROM. The ...
- 81
0
votes
0
answers
105
views
RISC-V vs C Code Comparison for Simple Multiply and Accumulate (MAC) Operation
We tried profiling a simple MAC operation using both RISC-V Vector (RVV) intrinsics and plain C code. Surprisingly, the C version performs better, even though the intrinsics code processes 16 ...
- 1
1
vote
0
answers
150
views
Function Call leads to infinite loop
I've been trying to get a program running on the QEMU emulator. The issue is that when I pass an empty string or a non-empty string to the print function, the program prints ABC indefinitely.
#[unsafe(...
0
votes
0
answers
62
views
RISC-V Spike: "Illegal Instruction" for Custom R-Type matmul - Match/Mask Not in Generated Dispatcher
I'm adding a custom R-type instruction matmul rd, rs1, rs2 to RISC-V Spike. Despite my efforts, I'm getting an "illegal instruction" error.
Toolchain & Assembly:
Modified riscv-binutils-...
4
votes
1
answer
97
views
GNU as recursive/loop macro expected output
In this assembly file below, the macro jump_table should automagically create ... a jump table to consecutively numbered labels like jump_0, jump_1, ... jump_<n>.
It seems there is no loop ...
- 3,500
2
votes
1
answer
128
views
Context switch in interrupt routine
I am writing an interrupt routine for RISC-V. Interrupts occur in U-mode and are handled in S-mode.
Upon an interrupt, I want to save the user execution context on the kernel stack of the thread that ...
- 173
1
vote
1
answer
101
views
Why __sync_or_and_fetch builtin in a loop renders as an endless loop with -O2 and -O3?
[SOLVED] Use __sync_fetch_and_or instead of __sync_or_and_fetch! The double amoor instruction maybe is still a bug.
[Disclaimer] This could be a bug in GCC but I am still new to RISC-V assembly to be ...
- 3,500
9
votes
3
answers
336
views
3D Morton code computation utilizing carry-less multiplication
This question arose specifically in the context of exploratory work for RISC-V platforms which may optionally support a carry-less multiplication instruction CLMUL. It would equally apply to other ...
- 27.1k
2
votes
1
answer
171
views
What Store/Store reordering do modern CPUs do in practice?
Aarch64 and RISC-V WMO seem to allow Store/Store reordering according to their formal specifications.
However, Store/Store reordering seems very tricky to perform in practice: the CPU would need to ...
- 579
1
vote
1
answer
117
views
How are interrupts handled when interrupts are disabled?
Say I switch from user mode to system mode by executing ecall, which disables interrupts by setting SIE bit in sstatus to 0.
What will happen to an interrupt that occurs while interrupts are disabled?
- 173
3
votes
1
answer
149
views
RISC-V naked function has extra nop and mv a0, a5
When you compile this RISC-V C function...
__attribute__ ((naked))
int foo() {
asm volatile("li a0, 1");
asm volatile("ret");
}
...it generates this assembly...
foo:
...
- 99.2k
1
vote
0
answers
110
views
RISC-V instruction equivalent to ARM's DSB execution barrier instruction for benchmarking to time loads?
I am writing a RISC-V assembly program whose goal is to assess the performance of main memory, in read access only for now.
I have thought about a simple benchmark code, that would load multiple ...
- 11
4
votes
1
answer
194
views
Why is RISC-V GCC uselessly reserving stack space in a function that returns a small struct?
This C source:
typedef struct {
unsigned long one;
unsigned long two;
} twin;
twin function( twin t ) {
return (twin){ 0,0 };
}
generates this assembly:
.file "p.c"
...
- 3,500
4
votes
1
answer
161
views
Why do dynamic value prints panic in my no_std kernel?
I'm trying to print dynamic values off in no_std Rust, specifically on the RISC-V architecture, but whenever I do, my kernel panics, and I can't even print the panic message because printing it panics ...
- 305
1
vote
1
answer
138
views
Do RISC-V kernel-space calling conventions exist?
RISC-V user-space function calls calling conventions are clear to me. It's also clear that a0-a5 are used to pass arguments to kernel and a7 to store system call number before an ecall. What I can't ...
0
votes
0
answers
86
views
Does disabling/enabling interrupts require memory barriers or similar memory ordering constraints?
AFAIK part of the reason why we need the C++11 memory model (and later patches/variants) is the fact we trade various things for single threaded executions to be fast, with only one main criteria i.e. ...
- 63
0
votes
0
answers
112
views
Using Merge Sort to Sort a Linked List with Inline RISCV ASM
I'm writing a Merge Sort to sort a linked list with inline RISCV asm, everything work fine until I start writing the part of lists merging.
Here is my function:
typedef struct Node {
int data;
...
- 1
1
vote
1
answer
161
views
GCC Linker error relocation error in RISCV 64 bit
This is my C code – Main.c :
static volatile unsigned int G_var;
void main()
{
G_var |= 1;
}
This is my linker file:
/*
Linker script
*/
OUTPUT_ARCH( "riscv" )
ENTRY( ...
- 194
-2
votes
1
answer
80
views
How do machine read the instructions of Risc-v [closed]
How do machine read the instructions?
for example:
if it is a R-type, machine first read the opcode to know the type of instruction,and base on the type, read the instruction from right to left,to ...
- 11
1
vote
1
answer
227
views
Why aren’t opcode and funct7 and funct3 a single 17-bit field?
In RISC-V, I want to know why opcode and funct7 and funct3 don't get together to be a 17-bits field?
- 11
2
votes
0
answers
111
views
Shared memory between RISCV vm (using Qemu) and host
I can't set correctly shared memory for Qemu RISCV emulation.
My intention is to create a portion of shared memory between Qemu RISCV emulator and the host server. I need this because my intention ...
- 21
-2
votes
1
answer
78
views
Is mulw faster than mul on riscv 64-bit platforms? [closed]
I wrote an unoptimized C source code for matrix multiplication, and I want to test the optimization capabilities of the Clang compiler.
void MatrixMul(unsigned int N, int *C, int *A, int *B) {
...
- 9
5
votes
1
answer
329
views
RISCV sleep (wfi) and interrupts
I am using RISCV based microcontroller in a project. There is inter-processor communication (IPC) via a mailbox. When the host writes to the mailbox, the RISCV gets an interrupt. I have an interrupt ...
- 466
2
votes
1
answer
154
views
Does risc-v require memory address 0 to be invalid?
So in risc-v, for a virtual memory system, I imagine it's up to the kernel to decide if 0 is a valid memory address or not? But for machine mode, or supervisor mode, is memory address 0 valid to ...
- 305
0
votes
2
answers
832
views
How to fix "unsafe attribute used without unsafe" in custom attribute macro?
project: https://github.com/xiaguangbo/picorv32_and_rust
error code：
program_picorv32ec/project/src/main.rs
#[picorv32asm::entry]
fn main() -> ! {
loop {}
}
error message：
$ cargo build
...
- 127
0
votes
1
answer
172
views
RISCV assembly 32bit multiplication without MUL giving incorrect result
I tried to implement unsigned 32 bit multiplication to be used on CH32V003 chip which doesn't have a hardware multiplier. I translated a code used for AVR to RISCV assembly (shift and add method) ...
3
votes
1
answer
107
views
Rust optimizes away all the interrupt/exception handlers from riscv-rt
I'm trying to build a simple app using riscv-rt for a riscv32imac target by following the steps from https://docs.rs/riscv-rt/0.14.0/riscv_rt/. What I need is a couple of external interrupt handlers. ...
1
vote
1
answer
116
views
raise Store/AMO page fault when trying write stack in xv6's trampoline
I'm trying to modify xv6 to make it a multi-thread system.One of the modification I made is that I need do some computing oprations in trampoline because I need every thread to find its unique ...
- 13
0
votes
0
answers
35
views
RISCV vector extension
Not able to execute a C program which has vector addition using RISCV.
I downloaded the gnu tool-chain and added the vector extension. But when I am running a sample C code which does vector addition, ...
0
votes
1
answer
108
views
Running test on Rocket core CPU - global variable initialized to 0 is unsuccessful, output wrong value instead
While I am benchmarking my Rocketcore CPU, I encountered failed Coremark benchmarking. After some debug, I reduce the issue scope to unsuccessful global initialization of 0 value. In Coremark, it will ...
- 119
0
votes
0
answers
30
views
Assembly round bracket syntax [duplicate]
I am following a build you own OS tutorial (https://operating-system-in-1000-lines.vercel.app/en/10-process#changes-in-the-exception-handler).
What does 4 * 1(sp) in the expression
sw gp, 4 * 1(sp) ...
- 561
0
votes
1
answer
154
views
Difference of 'software interrupt' and 'exception' in RISC-V
I'm reading privileged ISA manual of RISC-V, and I found that they strictly separate the 'interrupt' and 'exception' and 'trap'. In my understanding, the asynchronous event from outside is 'interrupt',...
- 1
1
vote
1
answer
234
views
How to set RISC-V `-march` for zig build
When cross-compiling for RISC-V with Zig I believe you do something like this:
pub fn build(b: *std.Build) void {
const target = b.resolveTargetQuery(.{
.cpu_arch = .riscv32,
.abi =...
- 99.2k
0
votes
0
answers
133
views
I am having a lab about quick sort in 'RISC-V'. I have done something but my recursive part kept buggy
I guess is stack pointer problem but I can't fix it. Here is my code:
.global _start
.data
array1: .word -5 24 -8 45 -15 24 11 7 0 125
hi: .word 9
lo: .word 0
newline: .asciz "\n"
space: ....
0
votes
0
answers
65
views
Problem adding custom MAC instruction with 4 operands to the RISCV architecture
I am trying to add a custom instruction which has 4 operands. It does multiply and accumulate (a*b+c) to the first 3 source registers and then store the result in the destination register. It ...
1
vote
2
answers
212
views
Discrepancy of `unsigned long` size between llvm and gcc in riscv32
I do not know if this is a bug or intended (I'm missing a flag). But in gcc unsigned long expands to uint32_t while in llvm it doesn't.
#include <stdint.h>
void test (uint32_t i);
void test (...
- 323
1
vote
1
answer
103
views
What kind of executable is produced by gcc wtih `-static-pie`?
The question is specific (but not limited to) to a bare-metal Risc-V code, I am trying to understand what would be required in order to compile a position-independent firmware binary. I tried to ...
- 18.7k
0
votes
0
answers
73
views
Risc-V jal instruction seems to make program hang
I am programming in a RISC-V 32I simulator called CompSim, and I am encountering an issue with the jal instruction in a specific part of my program. The program reads a multi-digit number from the ...
0
votes
0
answers
210
views
Why does my Linux kernel with OpenSBI not boot correctly when jumping to a new load address (0x80100000)
I used the following command to build the OpenSBI payload and Linux kernel image:
make PLATFORM=generic FW_FDT_PATH=$WORKLOAD_BUILD_ENV_HOME/dts/build/xiangshan.dtb FW_PAYLOAD_PATH=$RISCV_LINUX_HOME/...
- 119
0
votes
1
answer
159
views
Why won't my linker put .rodata after .text?
I want to put my .text section at 0x80200000, but despite my every attempt, .rodata refuses to move out of my way, leaving .rodata at 0x80200000 instead:
Sections:
Idx Name Size VMA ...
- 305