134 questions
0
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0
answers
68
views
How to setup approriate configs for single-core rocket-chip Gemmini Accelerator?
I'm buiding a single-core rocket chip, which use an Gemmini interface to do systollic array, and I use board Arty-Z7 to run demo on FPGA. My problem here is I don't know how to choose a suitable ...
- 1
0
votes
0
answers
40
views
Can I insert a folder (directory) instead of a file as a BlackBox in Chipyard?
I am trying to configure an MMIO Peripheral (= MMIO Accelerator, 11page) consisting of a 4x4 NoC in Chipyard. In this process, I would like to insert a SystemVerilog-based NoC as a BlackBox. However, ...
- 62.9k
2
votes
0
answers
87
views
RISC-V bare-metal simulation problem, increasing .rodata array size causes hang during DMA
I am trying to write data starting at a specific address (0x88000000) of the memory (simulated DRAM size is 256 MiB), once all data is written, the DMA unit is programmed using the MMIO registers. The ...
- 182
0
votes
0
answers
57
views
Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface. This MMIO device is intended to be a slave and the rocket-core as the master. For this, I created a ...
- 182
0
votes
1
answer
108
views
Running test on Rocket core CPU - global variable initialized to 0 is unsuccessful, output wrong value instead
While I am benchmarking my Rocketcore CPU, I encountered failed Coremark benchmarking. After some debug, I reduce the issue scope to unsuccessful global initialization of 0 value. In Coremark, it will ...
- 119
1
vote
1
answer
311
views
multiple definition of `bitbang_swd' when building rocket-chip tools
I am trying to build rocket-chip tools according to instructions here: https://github.com/chipsalliance/rocket-tools/blob/master/README.md
I face the following error:
/usr/bin/ld: src/.libs/libopenocd....
- 305
0
votes
1
answer
138
views
Rocket-Chip generator environment setup
I tried to set up the rocket-chip generator environment. I cloned the git repository and updated the submodules as follows:
$ git clone https://github.com/ucb-bar/rocket-chip.git
$ cd rocket-chip
$ ...
- 1,032
1
vote
0
answers
132
views
How to obtain emulator binary in latest rocket-chip using mill and chisel 5.0.0?
I've setup Chisel 5.0.0 and firtool as I explained in this other question. I also installed successfully mill and rocket-tools as instructed here and here.
This prepared the stage for getting the ...
- 319
0
votes
1
answer
219
views
Issue with Threads in embedded system
I have 4 Rocket RISC-V cores and each are connected to 4 identical accelerators. What I am trying to do is to use multithreading to run all or some of the accelerators at the same time and compare the ...
- 182
1
vote
1
answer
186
views
Try to compile and install rocket-chip generator but scala reports a constant pool index error
Here is the bug report:
macros.compile scala.reflect.internal.FatalError:
bad constant pool index: 0 at pos: 48461
while compiling: <no file>
during phase: globalPhase=<no ...
- 3,841
1
vote
1
answer
2k
views
RISC-V PMP instruction access fault when jumping to U mode
I am trying to use PMP on a 16-byte region to protect a specific memory region. However, I am getting an instruction access fault when jumping to U mode when the PMP configuration is enabled.
Details:
...
- 1
2
votes
1
answer
669
views
Generating verilog file for rocket chip
I am a beginner working with rocket chip generator for my project but I am not able to generate the verilog file for it and facing this error. I am using an apple M1 chip macOS. I started with cloning ...
- 11
0
votes
1
answer
225
views
Build rocket-tools for gcc-13
I'm following the instructions in rocket-chip v1.6 to install and run rocket-chip. As mentioned there, I need to install rocket-tools first (it's not mentioned what version of rocket-tools is ...
- 76
0
votes
1
answer
544
views
Rocketchip: make failing under /emulator and /vcs due to "mill: command not found"
Discussed in https://github.com/chipsalliance/rocket-chip/discussions/3492
Originally posted by AnuragMalwee September 20, 2023
Hi, I am building the rocket-chip project for the first time, and never ...
- 556
0
votes
1
answer
164
views
sbt test does not work and all the tests fail
I have installed rocket-chip and it needs chisel to compile i have also downloaded chisel , but when i run sbt test all the tests fail, am i doing something wrong . is there an alternative for sbt ...
- 1,378
0
votes
1
answer
108
views
How to export TileLink node to LazyModule's output and generate respective verilog file
I am trying to create a simple module with tilelink client connected to modules output. How to do it? Have been trying to figure it out for 20 hours at this, I am completly lost.
I am trying the ...
- 1
0
votes
1
answer
54
views
Rocket chip didn't work when using large array
I am simulating baremetal executables on Rocket chip with verilator. When I use a large array like
float a[3][224][224]
the simulation in verilator will not work successfully.
Here is my main.cpp:
int ...
0
votes
1
answer
131
views
Rocket Chip - Access Exception on Page Table Walk
I am trying to integrate a RoCC accelerator with RocketChip / Chipyard. Given a virtual address, the accelerator should translate it to a physical address, read some data from memory and then start a ...
- 96
0
votes
1
answer
44
views
Separate reset domain for RocketTile?
Is there a way to wire RocketTile to a separate (external) reset signal, so that the tile can be held in reset while the rest of the system is active?
The code seems to support a separate reset domain ...
- 324
0
votes
1
answer
162
views
(Rocketchip + Sifive-blocks UART) Unable to make use of system printf() function
I am currently working with the Rocket Chip repo to generate a 32-bit width microcontroller. I removed the debug module (The SimDTM or SimJTAG) for compiling on VCS 2014, so for debugging purpose I ...
- 119
0
votes
1
answer
203
views
Can I alter the testbench without re-make the Rocketchip core in verilator?
I am trying to work on Rocketchip simulation with Verilator that comes within the Rocket Chip Generator repo. From my understanding, Verilator will first take the scala files (in ./src/main/scala/) ...
- 66
0
votes
1
answer
67
views
How is data width determined for load/store instructions in Rocket Core?
I'm working on a project where we need to modify a Rocket-chip core with new instructions.
We're wondering: how does data width for load/store instructions is determined ?
For instance, LB/LH/LU have ...
- 1
2
votes
1
answer
495
views
Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error
I am trying to build a minimal example, of how to generate an AXI4Stream interface using Chisel and diplomacy. I am using the diplomatic interface already available in rocket-chip (freechips....
- 355
-3
votes
1
answer
489
views
How to synthesis Rocket-Chip on Vivado?
I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I ...
- 1
-2
votes
1
answer
161
views
Can you synthesize the RISC-V rocket chip test harness module?
After I setup the rocket-chip, it generated example top level Verilog. Can I synthesize the testharness.v module? I manually import the code into vivado, but got syntax error in SimDTM.v
(import "...
- 2,438
0
votes
1
answer
481
views
How to enable performance counters in Rocket Core
I am trying to enable performance counters in the Rocket core.
I don't see the implementation of mhpmevent3, mhpmevent4, mhpmcounter3, mhpmcounter4 in the RTL of the defaultConfig.
I see that ...
- 55
0
votes
2
answers
202
views
Git gets stuck during Quick Instructions in Rocket-chip
When I try the Quick Instructions in rocket-chip, it gets stuck.
After git submodule update --init --recursive, there is no more response, showing only:
Submodule 'fsf-binutils-gdb' (git://sourceware....
- 25
1
vote
1
answer
370
views
using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language
I want to use rocket chip to generate a axi4crossbar with 2 slave ports and 1 master port, here is my chisel source code
package empty
import chipsalliance.rocketchip.config.{Config, Parameters}
...
- 25
1
vote
0
answers
137
views
Documentation for RocketChip-generator
I recently started digging into the rocketchip generator because I want to use it for a project.
I am really new to chisel and the way that RocketChip is generated.
By now i figured out how I can ...
- 11
1
vote
1
answer
102
views
Scala syntax question in Rocket-chip config.scala
I just learned about the scalar to study rocket chips.
I see some strange codes in the Config.scala of Rocket-chip
abstract class Field[T] private (val default: Option[T])
{
def this() // 1st-this
...
- 15.9k
2
votes
0
answers
296
views
How to run multi-thread programs in rocket-chip?
I am trying to run multi-thread programs/benchmark in a rocket-chip SoC I generated from chipyard.
I generated the TutorialConfig SoC given in https://fires.im/isca22-slides-pdf/...
- 75
1
vote
1
answer
389
views
TIMESCALEMOD verilator error when attempting to add a new black box in chisel
I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator.
My changes pass chipyard's scala compilation phase in which the chisel ...
- 355
0
votes
1
answer
409
views
Adding a MMIO peripheral to a small rocket core
I have successfully added and simulated my MMIO perihperal coupled to a normal sized rocket core before.
But now I want to try to add it to a small core (so called TinyCore), and this is the part ...
- 355
0
votes
1
answer
132
views
Using values of loaded registers in rocket-chip custom instructions
I am trying to add a custom instruction to a freedom e300 rocket-chip.
The custom instruction is to perform an operation using the values of registers a0 to a7 that have been pre-loaded. (Load the ...
- 146
8
votes
1
answer
494
views
How to find the number of PLIC contexts?
I'm a SW developer trying to understand configuration of the RISC-V Platform-Level Interrupt Controller (PLIC) that's in a rocket-chip derived SoC in an FPGA. Please correct me if my terminology is ...
- 73.3k
0
votes
1
answer
132
views
Why does CLINT's timecmp have no reset?
I'm basing this off of Rocket-chip's implementation of CLINT. I don't believe this is in the RISC-V spec but the notion of CLINT shows up in a lot of RISC-V cores, so I've included the tag.
Currently, ...
- 355
1
vote
1
answer
68
views
Why would FifoFixer's `stall` signal go high forever?
I'm attempting to do these rather large DMA transfers over the frontbus to memory. The frontbus is ready and no other clients are contending for the front bus at the moment this occurs. My AXI client ...
- 355
0
votes
1
answer
118
views
reg_write64 MMIO register error in rocket chip
I am trying to write a 64 bit word to the MMIO register using the reg_write64
construct defined in mmio.h. Everything works fine as long as the wire that I map this register to in chisel land is not ...
- 406
0
votes
1
answer
569
views
How to connect a PCIe device to a chipyard design
I'm trying to connect a PCIe device to a chipyard design using the existing edge overlay for the VCU118 (slightly modified because I'm using a different board but this should not matter).
@michael-...
- 355
1
vote
1
answer
359
views
How to assign data to a register in chisel?
I initialized two registers in my accelerator like
val one = RegInit(0.U(5.W))
val two = RegInit(0.U(5.W))
If I have loaded a data to my rs1(R-type instruction) in my C test code, I wanted to assign ...
- 6,074
0
votes
0
answers
186
views
Executing programs on TinyCore (TinyRocketConfig)
I am trying to write executable programs to simulate using Verilator, but it seems like I am doing something wrong, as even the most simple program doesn't seem to run on the TinyRocketConfig.
The C ...
0
votes
1
answer
277
views
Unable to get Rocket Chip waveforms for GTKwaves
I want to run a program on Rocket core and observe all the signals in corresponding registers in GTKwave (e.g. PC, register file, ALU registers and wires etc.)
However, the only I get (both in ...
- 355
1
vote
1
answer
1k
views
Timescale missing on the module as other modules have it Verilator error
I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the basic GCD code. I then replaced the GCD with an ...
- 406
0
votes
1
answer
154
views
How can I generate AHB memory port in Rocket chip
I am trying to implement a Rocket chip SoC design; the SoC design will generate an AXI memory port by default. But I want to use the AHB memory port, and the Rocket chip doesn't have any configs for ...
- 355
1
vote
1
answer
788
views
Adding an MMIO peripheral to Rocket-chip as a submodule
I followed the MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up ...
2
votes
1
answer
757
views
Developing Generic AXI4 Peripheral with Chisel
I want to develop a generic AXI4 peripheral with Chisel. Can I use the Rocket-Chip's AMBA library for this purpose? I could only find the document in the link below on this subject;
MMIO-Peripherals
...
- 1,741
2
votes
0
answers
101
views
chisel Vec() in Bundle class cannot be implemented in Module class
The chisel version I'm using is 3.2.2.
When I try to create a Vec of member in a Bundle class, code is like,
class myIOBundle extends GenericParameterizedBundle {
val en = Vec(4, Output(Bool()))
...
- 21
2
votes
1
answer
98
views
In chisel, How to generate serval Module with different parameter?
I have a Module monit which has an parameter threshold , then I want to generate serval(e.g.8) Module monit in the wrapper with different threshold . But when I use
val monits = Seq.fill(8)(Module(new ...
- 568
0
votes
0
answers
100
views
Why adding more cores to simulate multi-threaded program increases the CPI?
Hello I'm using the Rocket Chip repository with Rocket Tools and while running some of the test on different chip configurations I've found this counter-intuitive behavior. I have a default chip with ...
- 53.4k
1
vote
1
answer
300
views
What are these `a.bits.user.amba_prot` signals and why are they only uninitialized conditionally in my HarnessBinder?
Context: I began using Chipyard about a month back to facilitate the building of a quick prototype using RISC-V cores on the VCU118. Chipyard was perfect, but required me to step up and learn Chisel ...
- 355