Say I switch from user mode to system mode by executing ecall, which disables interrupts by setting SIE bit in sstatus to 0.
What will happen to an interrupt that occurs while interrupts are disabled?
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1They are not handled, but also not ignored: they are simply delayed until the processor says its ready (by the software saying so). However, if some code ignores interrupts for too long, the risk is that some information could be lost. For example, if a second keyboard interrupt happen before the first one is serviced, that first keystroke will be lost. This means the interrupt handler (or any other code that runs with interrupts turned off) needs to restore interrupt handling with some alacrity.Erik Eidt– Erik Eidt2025-04-16 03:41:57 +00:00Commented Apr 16 at 3:41
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1 Answer
There is a concept of pending interrupt, that reflects by the value of SIP register (or MIP on machine mode). That interrupt remains pending until the global interrupt enable (SIE) is restored, at which point, if the interrupt source is still active (or its pending bit remains set), the processor will take the interrupt trap.
If multiple interrupts occur while interrupts are disabled, their respective pending bits are all set. RISC‑V hardware generally assigns priorities to interrupts, so when you re‑enable interrupts, the highest‑priority pending interrupt is taken first.
So, in short, the interrupts are queued and should be handled in priority-order, after your ecall handler exits (with sret or mret).
The actual delivery behavior may depend on the exact interrupt source (e.g., level‐sensitive versus edge‐triggered), but generally, interrupts are latched as pending rather than ignored.
There is also an option of having nested interrupts, means handling interrupts while the handler still executes, but that's rather different and more complicated story.
2 Comments
Eugene Sh.
he actual delivery behavior may depend on the exact interrupt source (e.g., level‐sensitive versus edge‐triggered), but generally, interrupts are latched as pending rather than ignored. - if we are talking about the "bare" RiscV core, the pending bit in
mip is pretty much the value of the corresponding hardware "pin" going into the core, so it will stay asserted as long as the pin is asserted. It is not latched. The latching logic is external to the core (that is PLIC or some other interrupt controllers).Eugene Sh.
That is, if the the
mip is asserted and de-asserted while mstatus.MIE is disabled (or the corresponding mask bit in mie), the interrupt won't be taken once mstatus.MIE is re-enabled.