How to make verilog is ready for CAD tools after build the VCS simulator

Question

I've built the VCS simulator successfully with some configuration (Default, DualCoreConfig, RoCCExampleConfig etc.) and get the desire files under vism/generated-src Now How Can I use/prepare this file to in CAD-tools (SYNOPSIS)

Do I need any processing to compile the Verilog file to run in CAD tools or how can I do this?

Thank you

I think "CAD" is referring to "computer aided design", not a specific tool. — Light
– Light, Commented Aug 20, 2020 at 11:03

seldridge · Accepted Answer · 2020-09-04 20:09:58Z

0

There is some documentation about this on the Rocket Chip README.

You primarily need to do two things:

Populate any memory blackboxes. You can either modify the included scripts/vlsi_mem_gen script to align with your memory compiler (or the memories generated by your memory compiler) or manually populate this blackbox. You can find the parameters of the blackboxed memories in a vsim/generated_src/*.conf file.
Run VCS with the SYNTHESIS variable defined.

If building Rocket Chip with the "hardfloat" floating point unit, you should enable retiming in your VLSI tools to get a decent clock rate (as indicated by this answer: https://stackoverflow.com/a/39006952/3870549).

answered Sep 4, 2020 at 20:09

seldridge

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