700 questions
0
votes
1
answer
52
views
Can Record class be used to create RegInit?
I am trying to use Record class to generate RegInit. This can help to dynamically create RegInit with other information in Module.
I am trying to use Record class to generate RegInit.
Here are my ...
- 13
1
vote
1
answer
293
views
Providing a simulation model for a chisel blackbox
I am trying to simulate a system using chisel 3. The system has a blackbox that has a verilog. The verilog code is not behavioural, it simply instantiate a module that the synthesizer configures.I ...
1
vote
1
answer
52
views
Copying a bundle into another bundle
Is there any way to copy all bits of a bundle into another bundle? Basically, I want to send out the same data into two outputs that would be connected to different receivers.
E.g:
io.out(1).bits.x :=...
- 151
1
vote
1
answer
102
views
Scala syntax question in Rocket-chip config.scala
I just learned about the scalar to study rocket chips.
I see some strange codes in the Config.scala of Rocket-chip
abstract class Field[T] private (val default: Option[T])
{
def this() // 1st-this
...
- 66
1
vote
1
answer
267
views
Is Chisel Counter more than 32 bits possible?
I declared a counter like this :
val MAXCOUNT = ((BigInt(1) << COUNT_WIDTH)-1)
val counterSize = log2Ceil(MAXCOUNT)
println("Maxcount -> " + MAXCOUNT + ", " + ...
- 3,901
1
vote
1
answer
198
views
How to test decoupled IO of bundle in chisel testers
I'm trying to implement a queue of bundles using chisel
class element extends Bundle{
val data=UInt(32.W)
}
class testQueue extends Module
{
val io = IO(new Bundle {
val in = Flipped(Decoupled(...
- 51
1
vote
1
answer
99
views
Chisel3: How can I remove Input and Output in Bundle definition
If I have
class ios extends Bundle{
val wen = Input(Bool())
val wdata = Input(UInt(8.W))
val rdata = Output(UInt(8.W))
}
With Flipped I can get something like
class flipped_ios extends Bundle{
...
- 105
1
vote
1
answer
146
views
How to use the empty signal of the Queue?
I'm using the Queue of the Chisel Lang in a design. Accessing the empty and full signals of the Queue could be beneficial, but since they're not part of the IO, I cannot use them. Is there any way to ...
- 151
2
votes
1
answer
82
views
How to publish Chisel package?
I made some chisel projects published on my github repositories.
All projects are initialized with chisel-template official example.
For the moment to use these as packages I have to «publish it local»...
- 3,901
2
votes
2
answers
247
views
Where does dut in Chisel Test get defined? (About Scala syntax)
I am trying to come up with a better title.
I am new in Chisel and Scala. Below there is a Chisel code defining and testing an module.
import chisel3._
import chiseltest._
import org.scalatest....
- 105
1
vote
0
answers
42
views
How to move sram to top hierarchy in Chisel3/Firrtl
I make a RISCV core with chisel3. However, when I want to tapeout the core, the SRAMs make a big problem. I should synthesize the logic first, and synthesize the top hierarchy with SRAM as blackbox.
...
- 136
0
votes
1
answer
370
views
Initializing IO with a bundle in Chisel 3.5
I am fairly new to Chisel, and is currently attempting to rewrite a Chisel project from Chisel 3.4 to 3.5. The issue I have faced is the project initializes IO()'s with a custom class that extends a ...
- 239
0
votes
1
answer
146
views
Why there is no verilog code of other module except ProgramCounter generated by chisel?
I'm writing a chisel project as follows: Chisel Project. When I tried to generate a verilog file by
object Elaborate extends App {
(new chisel3.stage.ChiselStage).execute(args, Seq(chisel3.stage....
- 311
0
votes
1
answer
132
views
Using values of loaded registers in rocket-chip custom instructions
I am trying to add a custom instruction to a freedom e300 rocket-chip.
The custom instruction is to perform an operation using the values of registers a0 to a7 that have been pre-loaded. (Load the ...
- 1
1
vote
1
answer
189
views
How to overcome fixedpoint division problem in chisel3?
When I am running a code for testing in fixedpoint, I am getting an error. Can anyone help me with the code???
Code:
import chisel3._
import chisel3.util._
import chisel3.experimental....
- 11
0
votes
1
answer
208
views
Scala Chisel. BlackBox with 2-d verilog ports
In my scala chisel project I need to insert system-verilog blackbox with 2-d arrays of ports. For example:
module something_bb(
input [`somtething_width-1 :0] something_i [`somtething_num-...
1
vote
0
answers
50
views
How to input a matrix in an format that can be computed by a systolic array in Scala?
As we know for the two-dimensional systolic array, except that the data of the first row is sent at the time of initialization, or say the first cycle, the following ones must be sent after a row/...
0
votes
1
answer
41
views
How to initial a 2 Dimensions matrix with independent number of rows and columns in Scala?
I've seen something like:
def matInit(n:Int):Array[Array[Int]]={
val maxval=5
val rnd=new Random(100)
Array.tabulate(n){_=>Array.tabulate(n){_=>rnd.nextInt(maxval+...
1
vote
1
answer
389
views
TIMESCALEMOD verilator error when attempting to add a new black box in chisel
I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator.
My changes pass chipyard's scala compilation phase in which the chisel ...
-1
votes
1
answer
207
views
what is the best practice to initialize a FIRRTL memory? [closed]
When making a FIRRTL register, it is possible to provide a "with: (reset => ...)" value used to initialize the register.
When making a FIRRTL memory (aka a dynamic register array), there ...
- 1,925
8
votes
1
answer
494
views
How to find the number of PLIC contexts?
I'm a SW developer trying to understand configuration of the RISC-V Platform-Level Interrupt Controller (PLIC) that's in a rocket-chip derived SoC in an FPGA. Please correct me if my terminology is ...
- 73.3k
0
votes
1
answer
118
views
reg_write64 MMIO register error in rocket chip
I am trying to write a 64 bit word to the MMIO register using the reg_write64
construct defined in mmio.h. Everything works fine as long as the wire that I map this register to in chisel land is not ...
- 406
1
vote
1
answer
165
views
Calling Dsptools produces a Chisel runtime error
I started to program in Chisel recently and I need to use dsptools for my project. However I am having issues to even have a very simple case working.
For example the code below:
package radix2
...
- 13
1
vote
1
answer
90
views
what is the idiomatic way to update *part* of a memory element in FIRRTL? this comes up when updating one entry of a line in a cache
Writing a register file in FIRRTL is straightforward: make a memory of machine words and read/write them.
However, when writing a cache, it is different: you typically have a cache line and when ...
- 1,925
0
votes
1
answer
102
views
Trouble understanding statement order in Chisel
Here is a simple module containing a down counter:
import chisel3.util.{Valid, DeqIO}
class Input(WIDTH : Int) extends Bundle {
val x = UInt(WIDTH.W)
}
class Output(WIDTH : Int) extends Bundle {
...
- 20.7k
1
vote
1
answer
92
views
How to specify a Chisel3 search path?
This may or may not be a duplicate of How to use chisel module as package.
Again, for scala/sbt/maven experts this may be obvious, for old school ASIC designers it's not:
I have project PROJ with ...
- 11
0
votes
1
answer
569
views
How to connect a PCIe device to a chipyard design
I'm trying to connect a PCIe device to a chipyard design using the existing edge overlay for the VCU118 (slightly modified because I'm using a different board but this should not matter).
@michael-...
- 1
1
vote
1
answer
84
views
Why is this local var not set correctly according to ChiselTest
I'm coming from Bluespec and not understanding this Chisel behavior. I have a simple Module:
class WhyFails extends Module {
val io = IO(new Bundle {
val operation = Input(UInt(2.W))
...
1
vote
1
answer
122
views
How to write a Muller C Element in Chisel Scala Language for async circuit?
When I wrote this :
class MullerC(val WIDTH: Int = 2) extends Module {
val io = IO(new Bundle {
val in = Input(Vec(WIDTH, Bool()))
val out = Output(Bool())
})
io.out := false.B
when (...
- 56
2
votes
1
answer
176
views
how to get a critical path / bottleneck analysis of FIRRTL code?
I have some FIRRTL and I want to get a critical path / bottleneck analysis of the code so as to maximize the clock rate by minimizing the critical path.
I can write a weighted topological sort myself, ...
- 1,925
1
vote
1
answer
360
views
How to assign data to a register in chisel?
I initialized two registers in my accelerator like
val one = RegInit(0.U(5.W))
val two = RegInit(0.U(5.W))
If I have loaded a data to my rs1(R-type instruction) in my C test code, I wanted to assign ...
- 13
1
vote
1
answer
773
views
Chisel Cannot reassign to read-only
This is a continuation from the other question i asked : Instanciation of a class doesn't work (Chisel/Scala)
Actually, I wanna print the "result" variable. I wrote this command : sbt ...
- 73
1
vote
1
answer
369
views
Instantiation of a class doesn't work (Chisel/Scala)
I got the following error:
java.lang.IllegalArgumentException: requirement failed: must be inside Builder context
issue when I write this on the terminal : sbt run
This is my code:
import chisel3._
...
- 73
2
votes
1
answer
495
views
Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error
I am trying to build a minimal example, of how to generate an AXI4Stream interface using Chisel and diplomacy. I am using the diplomatic interface already available in rocket-chip (freechips....
- 23
1
vote
0
answers
110
views
How can I build a fat jar to build my Chisel code with sbt-assembly?
I would like to build a fat JAR that can build my Chisel code. I have built these previously using Maven assembly:
https://github.com/hutch31/ChiselCodeGenerator
But I would like to get this working ...
- 145
2
votes
1
answer
144
views
what do "cmem", "infer", and "mport" mean?
I see the following FIRRTL code emitted by Chisel:
cmem mem : SInt<64>[8]
and
infer mport _T = mem[io.address], clock
NOTE: my memory object is named "mem".
However in the firrtl 1.5....
- 1,925
1
vote
0
answers
158
views
chisel3 report producing java.lang.NullPointerException
Here is the code that causes java.lang.NullPointerException:
val confidence = SyncReadMem(params.numEntries, UInt(params.confidenceBitsNum.W))
val s0_valid = io.mem.valid
val s0_index ...
- 11
2
votes
1
answer
265
views
How to correctly pass implicit parameters to a module?
I'm trying to pass implicit parameters to a submodule in an instantiated module. The implicit parameter is the config package defined in rocketchipenter link description here, I want to use the config ...
0
votes
1
answer
503
views
I can't import the class whose path is IDEA's source root file
Software: IntelliJ IDEA
OS: Ubuntu20.04.3 LST
Language: Scala Chisel
Here is my project path tree:
- src[sources root]
-- common
--- Extend.scala
-- NpcCore.scala
Extend.scala
package common
...
- 5
2
votes
1
answer
935
views
False "Combinational loop detected"
I'm getting a wrong "CombLoopException" when passing a complex Record (Bundle based on key-value pairs) as UInt and converting the UInt back to the Record by using asUInt() and asTypeOf(...)....
- 23
1
vote
1
answer
1k
views
Timescale missing on the module as other modules have it Verilator error
I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the basic GCD code. I then replaced the GCD with an ...
- 406
1
vote
1
answer
68
views
Why would FifoFixer's `stall` signal go high forever?
I'm attempting to do these rather large DMA transfers over the frontbus to memory. The frontbus is ready and no other clients are contending for the front bus at the moment this occurs. My AXI client ...
- 355
0
votes
1
answer
479
views
ChiselTest - expect a bit value in a UInt
Per this: https://github.com/chipsalliance/chisel3/issues/2439
I've decided to change all Vec[Bool] to UInt where possible. One feature of a Vec[Bool] is that testing the values of each bit is simple.
...
- 1,581
1
vote
1
answer
104
views
Bundle using Mux
I want to use Mux to choose bundle
enter code here
class ComIO extends Bunlde {
val in = Input(UInt(32.W)
val in = Input(UInt(32.W)
}
class EntIO extends Bundle {
val com = new ComIO
}
class Ent ...
0
votes
1
answer
395
views
How to write nested fsm in Chisel like SpinalHDL does?
I've found that SpinalHDL has some powerful and elegant ways to describe a rather complicated fsm. I wonder if it's possible to construct a FSM lib (like SpinalHDL has done) in Chisel?
p.s. I'm not ...
1
vote
1
answer
788
views
Adding an MMIO peripheral to Rocket-chip as a submodule
I followed the MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up ...
- 319
1
vote
1
answer
770
views
How to specify the main class (in the root directory) for Mill to run?
I am new to the sbt and mill, and I am practicing to use both tool to build the chisel (scala project). View this github repo as a reference, I am wondering to know how to write the mill-version build....
- 11
4
votes
1
answer
112
views
How does a missing boolean operator still compile?
I have code like this:
val pop: Bool = (
(fsm === Fsm.None && canPop) ||
(fsm === Fsm.Some && canPop && fooBar)
(fsm === Fsm.Other && canPop && ...
- 1,581
0
votes
1
answer
451
views
How can I test a Chisel3 BlackBox?
I have the following test harness for a module defined in Verilog:
class TestMCQDiv extends FlatSpec with ChiselScalatestTester with Matchers {
behavior of "MCQDiv"
// Dependent ...
- 187
3
votes
1
answer
539
views
How to create a Vec literal from a Seq[Bool]
For testing inputs/outputs specified as vectors, I need to be able to programmatically create the desired Vec[Bool] for poke and expect. Seq[Bool] is a convient structure to create either directly (e....
- 1,581