Stage Placement Guidelines

#Breakwater wall - Placing of Armour Rock Layer The placement of armour rock shall conform to the following international guidelines such as CIRIA C793, PIANC, and USACE EM 1110-2-2904: #A) Armour units shall be individually and carefully placed to form a dense, well-interlocked layer, ensuring that each rock is securely restrained by surrounding stones to prevent displacement under hydraulic loading. #B) Placement shall begin from the structure’s toe and progress upwards toward the crest in a controlled and sequential manner. Each unit shall be lowered and positioned individually using appropriate lifting equipment. #C) Armour rocks shall not rely solely on frictional resistance in a single plane for their stability; interlocking with adjacent units must ensure multidirectional resistance to movement. #D) Bulk dumping, end-tipping from trucks, bulldozing, or direct discharge from hoppers or barges into final position shall not be permitted. All placement operations shall ensure precise control over rock orientation and interlock. #E) Rock units shall be placed in a random, yet stable configuration, ensuring a minimum of three-point contact with adjacent units, in accordance with the design lines, levels, and tolerances as indicated in the construction drawings. #F) The finished armour slope surface shall exhibit a rough, irregular, and angular profile to enhance wave energy dissipation and minimize reflection. #G) Rocks shall generally be oriented with their longest dimension perpendicular to the slope face. The armour layer shall consist of at least two rock thicknesses, unless specified otherwise in the project drawings. #H) Small stones shall not be used to wedge or chock larger armour units, nor to fill gaps smaller than 0.50Dn₅₀ (where Dn₅₀ = nominal median diameter). Proper interlocking must be achieved using appropriately graded armour. #K) Armour units shall not be dropped into position under any circumstances. Controlled placement is mandatory to preserve the integrity of individual rocks and the overall structure. #L) Continuous joints or linear voids between adjacent rocks are not acceptable. Placement must ensure staggered and irregular contacts to prevent structural weakness. #M) Rocks found to be fractured or damaged during or after placement shall be removed and replaced at the Contractor’s expense. Armour gradation shall conform to specified grading curves and remain consistent throughout the structure. #N) The Contractor shall conduct joint underwater inspections with the Engineer—by diver or remotely operated vehicle—to confirm accurate and stable placement of submerged armour layers.

🚀 Sharing insights on Physical Design Placement: My Placement Notes. Excited to unveil a comprehensive guide delving into the realm of Placement in physical design. This compilation stems from hands-on experience navigating practical hurdles using ICC2 commands. 💡 Inside My Notes: ✅ Handling macro placement to prevent timing violations and congestion. ✅ Tackling high fanout net synthesis (HFNS) by implementing buffer insertion and cloning. ✅ Resolving scan chain reordering issues to improve timing and minimize wire length. ✅ Addressing timing DRVs like max transition, max capacitance, and max fanout using strategic fixes like cell sizing, buffering, and VT swapping. ✅ Managing congestion with advanced techniques like partial blockages, cell padding, and keepout margins. 📂 What’s Inside: 1️⃣ A comprehensive breakdown of placement stages. 2️⃣ Real-time problem-solving techniques for critical design challenges. 3️⃣ Commands and tips to optimize placement for better timing, power, and area. 💡 This file isn’t just a technical guide—it’s a culmination of real-world problems I faced and how I resolved them, ensuring you gain practical insights. 💼 Why This Guide Holds Significance: Placement stands pivotal in PnR, with accurate execution saving hours of debugging and revisions. Consolidating my insights into this resource to smoothen your journey. 👉 Share your toughest placement challenge in physical design in the comments below. Let's engage in an idea exchange! #PhysicalDesign #Placement #VLSI #PNR #EDA #EngineeringJourney #ChipDesign #LearningTogether

12. #PLACEMENT - Part1 Inputs of Placement are Netlist, SDC, Physical and logical libraries, Tech file, Floorplan and Power plan DEF file. #Definition:              It is the process of placing the standard cells within the core boundary in the legalized positions. The goal of this stage is to place the cells with minimal congestion and best timing. #Strategies: 1. Timing-driven placement – The tool tries to reduce the RC values to meet the timing 2. Congestion-driven placement: The Tool tries to spread the cells when the density of cells is high to reduce congestion. 3. Area-driven placement – Using AOI, and OAI cells instead of AND-OR-AND cells to reduce area utilization. 4. Power-driven placement – Swapping LVT cells with HVT, and SVT cells will help to reduce the leakage power. #Stages: 1.     #Global_Placement / #Coarse_Placement Standard cells are placed in the appropriate locations according to timing, congestion, and connectivity but they don’t fall on the placement grid and may overlap with each other. 2.     #Detail_Placement / #Legalization The tool will move the standard cells to legalized positions and eliminate the overlapping of cells. During this process of legalization, additional delays may be added to the nets and can cause new timing violations. 3.     Optimization Techniques w.r.t Timing 1. #Vt_swap – Swapping the standard cells based on their doping concentration to reduce the delay. There are 3 types of cells based on Vt. They are 1.     HVT – Hight threshold voltage 2.     LVT – Low threshold voltage 3.     SVT – Standard Threshold voltage If standard cells have high doping concentration then it requires less time to Turn ON which is its propagation delay. Doping concentration – LVT > SVT > HVT So, the HVT cells in the critical timing paths are swapped with LVT cells. Trade-offs – LVT cells exhibit more leakage when compared to HVT, and SVT cells. 2. #Upsizing – Increasing the (W/L) ratio of the standard cells to improve the timing. By increasing the size of the cell, the resistance of it gets reduced which will improve the timing. Drive strength – 3X > 2X > 1X Replacing the 1X cells with 3X cells will improve the timing. Trade-offs – 3X cells will occupy more space compared to 1X, 2X cells as the area increases. 3. #Buffer Insertion – Buffers are inserted in long nets to reduce the RC delays. These buffers/repeaters are used to reconstruct the signal that will improve the transition of the cells and nets attached to it. This will finally improve the timing of the design. 4. #Cloning – It is the optimization technique by replicating the identical cells to the same inputs as the original cells which divides the fanout load and improves timing. 5. #Logic_restructuring – It is the rearrangement of logic to meet the timing of critical paths in the design. Placing NAND gate instead of AND, NOT gates.